The present invention relates to sense amplifier power supply circuits of semiconductor memory devices, and more particularly to a sense amplifier power supply circuit for improving the performance by rapidly supplying a power source of a sense amplifier.
Recently, the development of technology has demanded a semiconductor memory device of large capacity. A sense amplifier power supply circuit is a sense amplifier in which a power supply line is most suitably arranged in the memory device, and is used to accommodate a memory of large capacity within small size. Since a conventional sense amplifier should widely array the power supply line according to a tendency toward the large capacity of the memory, the memory device is increased in size, and has become an disadvantage in its construction.
FIG. 1 shows a conventional sense amplifier circuit. A power source is supplied to sense amplifiers by power supply lines PL(PR) and NL(NR). FIG. 2 is a voltage waveform chart of the conventional sense amplifier circuit of FIG. 1. Hereinafter, the top and bottom portions of the sense amplifier circuit of FIG. 1 will be regarded as left and right sides, respectively. In the left side of the sense amplifier circuit, a field effect transistor PMOS1 has the source connected to a power voltage Vcc, the gate connected to a signal P-SW, and the drain connected to sense amplifiers through a left PMOS cell block power supply line PL. A field effect transistor NMOS1 has the source connected to a ground voltage Vss, the gate connected to a signal N-SW, and the drain connected to the sense amplifiers through a left NMOS cell block power supply line NL.
In the right side of the sense amplifier circuit, a field effect transistor PMOS2 has the source connected to the power voltage Vcc, the gate connected to a signal /P-SW, and the drain connected to sense amplifiers through a right PMOS cell block power supply line PR. A field effect transistor NMOS2 has the source connected to the ground voltage Vss, the gate connected to a signal /N-SW, and the drain connected to the sense amplifiers through a right NMOS cell block power supply line NR.
In operation, the power source is supplied to each sense amplifier (S/A) array as follows. The power voltage Vcc is supplied through the power wiring of the power supply lines PL and PR, and the ground voltage Vss is supplied through the power wiring of the power supply lines NL and NR. That is, the transistors PMOS1 and PMOS2 respectively supply the power voltage Vcc to the power supply lines PL and PR by switching the power voltage Vcc, thereby supplying the power voltage Vcc to the entire power wiring of the sense amplifier. The transistors NMOS1 and NMOS2 respectively supply the ground voltage Vss to the power supply lines NL and NR by switching the ground voltage Vss, thereby activating the sense amplifiers of the sense amplifier array.
As shown in FIG. 2, the signal P-SW of the memory array activated by addresses is set to logic "low" from logic "high", and then, the transistor PMOS1 is turned on, supplying the power voltage Vcc to the power supply line PL. Simultaneously, the signal N-SW is set to logic "high" from logic "low", and then, the transistor NMOS1 is turned on, supplying the ground voltage Vss to the power supply line NL. Therefore, the power supply lines PL and NL are as shown in FIG. 2, and the sense amplifiers connected between the power supply lines PL and NL can begin sensing operation. The power supply lines PR and NR of an inactivated memory array are maintained at a voltage of Vcc/2 and thus the sense amplifiers connected therebetween are maintained at an inactivated state.
Thus, since the above circuit having the sense amplifier power supply lines of an open loop state supplies current for operating the sense amplifier only by the power supply lines PN and NR (or PR and NR), there occurs a voltage drop by a resistor R of the wiring in the memory device having large instantaneous current during the sensing operation. This can be represented by the following equation: EQU v(t)=i(t).times.R
where v(t) is a voltage drop, i(t) is instantaneous current, and R is a resistor of the power wiring.
If the voltage drop occurs, since the sensing performance of the sense amplifier is deteriorated and the operating speed is lowered. In order to maintain the voltage drop of an appropriate level, the instantaneous current i(t) or the resistor R should be small. As one method for reducing the instantaneous current i(t), the number of sense amplifiers connected to the power supply line should be reduced. However, such a method leads to an increase in the number of memory array blocks and thus the device size should be increased. A method for reducing the resistor R of the power wiring also brings about an increase in the device size.